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Custom Compiler™ is Synopsys’ full-custom solution that features the pioneering visually-assisted automation flow to speed up common design tasks, reduce iterations and enable reuse. Tuned for rapid implementation of FinFET-based mixed-signal circuits, Custom Compiler is ideally suited to tackle tough advanced-node custom design challenges.

DC Ultra includes innovative topographical technology that enables a predictable flow resulting in faster time to results.Topographical technology provides timing and area prediction within 10% of the results seen post-layout enabling designers to reduce costly iterations between synthesis and physical implementation. DC Ultra also includes a scalable infrastructure that delivers 2X faster runtime on quad-core platforms.

Signoff users have a few key requirements for their signoff tool of choice: runtime and capacity to handle their largest chip size requirements, efficient multi-scenario analysis to verify timing across all corners and modes, margin control to reduce over-design and maximize chip performance, and accuracy to ensure correlation to silicon.

The Synopsys PrimeTime® Suite addresses these requirements by delivering fast, memory-efficient scalar and multicore computing, and distributed multi-scenario analysis and ECO fixing, while using variation-aware Composite Current Source (CCS) modeling that extends static timing analysis (STA) to include crosstalk timing, noise, power and constraint analysis

DC Ultra includes innovative topographical technology that enables a predictable flow resulting in faster time to results.Topographical technology provides timing and area prediction within 10% of the results seen post-layout enabling designers to reduce costly iterations between synthesis and physical implementation. DC Ultra also includes a scalable infrastructure that delivers 2X faster runtime on quad-core platforms.

Signoff users have a few key requirements for their signoff tool of choice: runtime and capacity to handle their largest chip size requirements, efficient multi-scenario analysis to verify timing across all corners and modes, margin control to reduce over-design and maximize chip performance, and accuracy to ensure correlation to silicon.

The Synopsys PrimeTime® Suite addresses these requirements by delivering fast, memory-efficient scalar and multicore computing, and distributed multi-scenario analysis and ECO fixing, while using variation-aware Composite Current Source (CCS) modeling that extends static timing analysis (STA) to include crosstalk timing, noise, power and constraint analysis

StarRC™ is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys’ Galaxy™ Design Platform, it provides a siliconaccurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal and memory IC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16nm, 14nm, 10nm, 7nm, and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification.

The IC Compiler™ place and route system is a single, convergent, chip-level physical implementation tool. It includes flat and hierarchical design planning, placement, clock tree synthesis, routing and optimization, manufacturability, and low-power capabilities that enable on schedule delivery of advanced designs. For Synopsys’ latest place-androute system refer to IC Compiler II.

Sentaurus is a suite of TCAD tools which simulates the fabrication, operation and reliability of semiconductor devices. The Sentaurus simulators use physical models to represent the wafer fabrication steps and device operation, thereby allowing the exploration and optimization of new semiconductor devices.

The Sentaurus TCAD tools work seamlessly and can be combined into complete simulation flows in 2-D and 3-D.

Sentaurus TCAD supports silicon and compound semiconductor technologies, covering a broad range of semiconductor applications.

SaberRD is an intuitive, integrated environment for designing and analyzing power electronic systems and multi-domain physical systems. With the proven Saber® simulation technology at its core, SaberRD combines ease of use with the power to handle today’s complex electrical power problems, allowing engineers to explore design performance, optimize robustness and assure system reliability for a broad range of generation, conversion and distribution applications. SaberRD’s true multi-domain physical modeling capability and unmatched analysis capabilities provide engineers with a virtual prototyping platform that supports complete system design. With an intuitive and flexible user interface for casual and expert users alike, SaberRD accelerates design for engineering organizations in automotive, aerospace, defense and industrial power.

Click here to view the SaberRd training videos

DC Ultra includes innovative topographical technology that enables a predictable flow resulting in faster time to results.Topographical technology provides timing and area prediction within 10% of the results seen post-layout enabling designers to reduce costly iterations between synthesis and physical implementation. DC Ultra also includes a scalable infrastructure that delivers 2X faster runtime on quad-core platforms.

Signoff users have a few key requirements for their signoff tool of choice: runtime and capacity to handle their largest chip size requirements, efficient multi-scenario analysis to verify timing across all corners and modes, margin control to reduce over-design and maximize chip performance, and accuracy to ensure correlation to silicon.

The Synopsys PrimeTime® Suite addresses these requirements by delivering fast, memory-efficient scalar and multicore computing, and distributed multi-scenario analysis and ECO fixing, while using variation-aware Composite Current Source (CCS) modeling that extends static timing analysis (STA) to include crosstalk timing, noise, power and constraint analysis

StarRC™ is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys’ Galaxy™ Design Platform, it provides a siliconaccurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal and memory IC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16nm, 14nm, 10nm, 7nm, and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification.

The IC Compiler™ place and route system is a single, convergent, chip-level physical implementation tool. It includes flat and hierarchical design planning, placement, clock tree synthesis, routing and optimization, manufacturability, and low-power capabilities that enable on schedule delivery of advanced designs. For Synopsys’ latest place-androute system refer to IC Compiler II.