Job Description

• IP Lead for High Speed SERDES Designs (such as USB2, USB3/PCIe, SATA, DP, HDMI, SGMII, QSGMII, MIPI M-PHY, Multi-protocol SERDES)
• Creating Data Sheet, Design doc, architecture, Micro architecture doc and RTL design
• Opportunity to work in cutting edge nodes such 10/16nm in multiple foundries namely TSMC/UMC/SMIC, etc
• Interact and drive internal Verification, Analog, Layout and Silicon Validation team to build world class IP
• Customer support (including on-site support)
• Engage in pre-sales along with Product Engineering and Marketing teams
• Manage/Mentor a small team with highly talented engineers to drive the IP development activities

Desired Skills and Experience

• Thorough understanding of USB2, USB3/PCIe protocols and UTMI/PIPE specifications
• Thorough understanding of USB OTG/ADP/BC is a plus
• Understanding of MPHY, DP, HDMI, SATA, SGMII/QSGMII/XAUI protocol and corresponding MAC-PHY interface is a plus
• Experience in RTL Compiler, EDI (Encounter, Encounter Test, Voltus, TEMPUS) is a plus
• Experience in IP-XACT/SystemRDL, AMBA-AHB/AXI/APB, JTAG is a plus
• Technical project management skill is required

Job Description

Synthesis and Timing closure on 28nm/20nm/16nm technologies based designs

• Co-work with RTL engineers and DFT engineers to consolidate modem subsystem timing constraints along with toplevel SOC requirements
• Verify timing constraints with CCD
• Develop floor-planning and CTS guidelines for layout
• Analyze pre-layout and post-layout timing, develop timing ECOs, and work closely with layout engineers to achieve full chip timing closure
• Performance in-house quality check before P&R and after P&R.

Desired Skills and Experience

• BS or M.Tech degree in EE or related
• Minimum 3 years working experience with top/block level timing closure (STA), timing closure methodologies.
• Good experience in EDA tools : Synopsys DC/DCT/DCG and Primetime
• Good understanding of Deep Sub Micron topics
• Ability to understand clock tree designs
• Well versed with tcl / Perl script.
• Ability to communicate effectively with multiple global cross-functional teams
• Enthusiastic and ability to be an independent player and also work in team

Job Description

Strong back ground of ASIC physical design: Floor planning, P&R, extraction, IR Drop Analysis, timing and signal Integrity closure and experience on Cadence or Synopsys or Magma Physical Design Tools

Desired Skills and Experience

• MTechs (ECE/CS/Communication Systems)from premiere institutes with 0-2 years experience.
• Strong back ground of ASIC physical design: Floor planning, P&R, extraction, IR Drop Analysis, timing and signal Integrity closure
• Extensive experience and detailed knowledge in Cadence or Synopsys or Magma Physical Design Tools
• Expertise in scripting languages such as PERL, TCL strong physical verification skill set. Static timing analysis in Primetime or Primetime-SI
• Desired skills- Expertise in full chip physical design
• Provide technical guidance, mentoring to Physical Design Engineers Interface with front-end ASIC teams to resolve issues
• Low Power Design - Voltage islands, power gating, substrate-bias techniques. Timing closure on DDR2/DDR3/PCIE interfaces
• Should be able to do top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks(DRC), and Logical vs. Schematic (LVS) checks, antenna checks
• Should have worked on 65nm or lower node designs with advance low power techniques such as voltage islands, power gating and substrate-bias
• Experience in backend flow including physical design, timing analysis to final tape out in 28nm and below. Hands on experience in standard backend tool flows is a must.
• Excellent communication skill

Job Description

Strong back ground of ASIC physical design: Floor planning, P&R, extraction, IR Drop Analysis, timing and signal Integrity closure and experience on Cadence or Synopsys or Magma Physical Design Tools

Desired Skills and Experience

MTechs (ECE/CS/Communication Systems)from premiere institutes with 0-2 years experience.

• Strong back ground of ASIC physical design: Floor planning, P&R, extraction, IR Drop Analysis, timing and signal Integrity closure
• Extensive experience and detailed knowledge in Cadence or Synopsys or Magma Physical Design Tools
• Expertise in scripting languages such as PERL, TCL strong physical verification skill set. Static timing analysis in Primetime or Primetime-SI.
• Desired skills- Expertise in full chip physical design
• Provide technical guidance, mentoring to Physical Design Engineers Interface with front-end ASIC teams to resolve issues
• Low Power Design - Voltage islands, power gating, substrate-bias techniques. Timing closure on DDR2/DDR3/PCIE interfaces
• Should be able to do top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks(DRC), and Logical vs. Schematic (LVS) checks, antenna checks
• Should have worked on 65nm or lower node designs with advance low power techniques such as voltage islands, power gating and substrate-bias
• Experience in backend flow including physical design, timing analysis to final tape out in 28nm and below. Hands on experience in standard backend tool flows is a must.
• Excellent communication skill