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Current Entry & Senior Level Openings

RTL Design Engineer – 0 to 8 yrs

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ASIC Verification Engineer – 0 to 8 yrs

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Synthesis & Timing Closure Engineer – 0 to 8 yrs

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Physical Design Engineer – 0 to 8 yrs

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Analog / Full custom Layout Engineer –0 to 8 yrs

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Memory Layout Engineer – 0 to 8 yrs

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Standard Cell Layout Engineer – 0 to 8 yrs

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Leadership Team

Nanochip Solutions leadership team comes with decades of industry expereince. The leadership team comprises of professionals with over 100 man years experience in the Areas of VLSI and Embedded Systems spanning multiple process nodes and design methodologies. The key members were involved in the development of design flows for multi billion transistor designs And many successful tapeouts and design wins to their credit.

Its the technical acumen of the leadership team which guides the policies of the company in operations, Customer engagement, training and employee retention, HR and strategic relationships.

Nanochip recognizes the value of a strong engineering workforce and invests heavily in employee training.