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Current Entry & Senior Level Openings

RTL Design Engineer – 0 to 8 yrs

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ASIC Verification Engineer – 0 to 8 yrs

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Synthesis & Timing Closure Engineer – 0 to 8 yrs

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Physical Design Engineer – 0 to 8 yrs

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Analog / Full custom Layout Engineer –0 to 8 yrs

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Memory Layout Engineer – 0 to 8 yrs

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Standard Cell Layout Engineer – 0 to 8 yrs

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Services

The company specializes in providing design enablement services and technology solutions in the following areas.

  1. Library Development – Standard Cells, Memory Cells and IO Cells
  2. Analog IP Development – Circuit Design & Full Custom Layout Design
  3. Digital ASIC Design – RTL to GDSII – RTL Design, Synthesis, Simulation, Verification, Static Timing Analysis, Gate Level Simulation, Physical Design
  4. Analog & Mixed Signal SoC Design Solutions
  5. PDK Development and Qualification
  6. VLSI CAD & Design Automation

Foundry Exposure : TSMC, IBM, UMC, Chartered Semi, Magnachip, and many captive fabs

Process / Technolgy Nodes : CMOS / Bipolar / BiCMOS From 0.5u down to 90nm / 65nm / 45nm / 32nm / 28nm

EDA Tools Expertise : Cadence, Synopsys, Magma, Mentor & other Industry Standatrd tools

Our experts provide solutions related to PDK development and Qualification, VSLI CAD and Design Automation solutions, Standard Cell design and characterization, Physical Verification and Parasitic Extraction solutions using Synopsys, Cadence and Mentor Graphics tool suites.

Our engineers are working on many projects from RTL to GDS they exibit a low TTP ©.